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| V370PDC Rev. A0 High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit * Fully compliant with PCI 2.2 specification target interface * Multiplexed or Non-multiplexed 8-, 16-, or 32-bit generic peripheral bus interface * Support up to 1 Gbyte of SDRAM * Support up to 2 single banks or 1 dual bank industrial standard 168-pin PC SDRAM DIMM * Support up to 1Kbyte of burst access from PCI * Up to 5 programmable chip select for peripheral strobe generation * Large On-Chip FIFOs using V3's unique DYNAMIC BANDWIDTH ALLOCATIONTM architecture * Buffered PCI clock output * Hot Swap Ready (PICMGTM Hot Swap Specification) * Implementation of PCI Bus Power Management Interface Specification Version 1.0 * Initialization through PCI or serial EEPROM * Programmable PCI and local interrupt management * Two 32-bit General Purpose Timers * Up to 66 MHz local bus clock with asynchronous PCI clock up to 33MHz * 3.3V operation with 5V tolerant inputs * Industrial Temperature Range (-40C to +85C) * Low cost 160-pin PQFP package The V370PDC PCI SDRAM Controller simplifies the design of PCI based memory sub-systems. System designers can replace many lower integration support components with this single, high-integration device saving design time, board area, and manufacturing cost. The V370PDC from V3 Semiconductor is a high performance PCI SDRAM Controller with integrated peripheral control unit operating at up to 66 MHz local bus speed. It features multiple address translation units from PCI which allow designers the freedom to customize their local address space. Access latency of slower peripherals are absorbed through the large OnChip FIFOs. The peripheral bus provides low latency access to SDRAM. The peripheral control unit on the V370PDC also performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals. The peripheral bus can also be tri-stated through a simple hand-shaking protocol to allow other local bus masters control of the bus. The SDRAM Controller connects the PCI bus through on-chip FIFOs to SDRAM arrays of up to 1 Gbytes in size. The fully programmable SDRAM controller also supports the use of Enhanced SDRAM to achieve even greater performance. Burst accesses of up to 1 Kbyte from PCI is supported. The two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes such as retriggerable or oneshot. Interrupts for a real time OS can be easily generated by the system heartbeat timer. A watchdog timer is also provided for graceful recovery from catastrophic program failures. Interrupt requests for all on-chip peripherals are managed by the Interrupt Control Unit. Additionally, off-chip interrupts can be routed to the Interrupt Control Unit. The V370PDC is packaged in a low-cost 160-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 66MHz speed grade. TYPICAL APPLICATION PCI-to-ISA Conversion Application ISA Conversion Logic PCI Target Only Application SRAM/ FLASH V370PDC V370PDC SDRAM and PROM SDRAM Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 1 V3 Semiconductor reserves the right to change the specifications of this product without notice. V370PDC is a trademark of V3 Semiconductor Inc. All other trademarks are the property of their respective owners. V370PDC This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V370PDC. Detailed functional information is contained in the User's Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design. 1.0 Product Codes Table 1: Product Codes Product Code V370PDC-66 REV A0 Package 160-pin EIAJ PQFP Frequency 66MHz 2.0 Pin Description Table 2 below lists the pin types found on the V370PDC. Table 3 describes the function of each pin on the V370PDC. Table 2: Pin Types Pin Type PCI I PCI O PCI I/O PCI I/OD I/O8 I/OD I O2 O8 O12 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 8mA output drive. TTL input with open drain output. TTL input only pin. TTL output pin with 2mA output drive. TTL output pin with 8mA output drive. TTL output pin with 12mA output drive. Description 2 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC Table 3: Signal Descriptions PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME Type PCI I/O PCI I PCI I/O PCI I Z Ra Z Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Z Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. Z Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. PCLK provides timing for all transactions on the PCI bus. SDRAM and Peripheral Bus Interface Signal CLKIN CLKOUT DCS[3:0] MA[14:0] RAS Type I O12 O8 O12 O12 X Z Z Z R Local clock input Buffered PCI clock output SDRAM Chip Select SDRAM Memory Address (also, A[16:2] for peripheral access). MA[14:13] are typically used for BA[1:0] SDRAM Row Address Strobe Description IRDY PCI I TRDY PCI O STOP PCI O Z DEVSEL PCI O Z IDSEL PCI I PERR PCI I/O SERR PCI I/OD Z PCLK PCI I Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 3 V370PDC Table 3: Signal Descriptions (cont'd) CAS MWE MAD[31:0] DQM[3:0] O12 O12 I/O8 O8 Z Z Z Z SDRAM Column Address Strobe SDRAM Memory Write Enable SDRAM and peripheral bus data SDRAM Data Mask (these act as MBE[3:0], A[1:0] for peripheral access) Peripheral bus arbitration input: Treated as bus request input when V370PDC is the primary bus master. When V370PDC is the secondary bus master, this input acts as bus grant. Peripheral bus arbitration output: Treated as bus grant output when V370PDC is the primary bus master. When V370PDC is the secondary bus master, this output acts bus request. Address Latch Enable: used to latch the address on MAD[31:0] during the address phase of a peripheral bus access. Asserted low to indicate the beginning of a bus cycle. Burst last. Data ready. Z Z Z Z Z Write/Read. Serial EEPROM Data Serial EEPROM Clock Multi-purpose I/O that can be configured for many functions General purpose interrupt inputs/outputs: may be used for either PCI or local processor interrupts Mode and Reset Signal RSTIN Type I R Description Reset Input: Active low reset input used to initialize all internal functions of the chip. Reset Output: Driven active when the input reset is driven active. Driven inactive when the RSTOUT bit in the system register is set. The RSTOUT signal is synchronous to the rising edge of CLKIN. PCI Precharge Bias: This signal is driven low to activate the onchip precharge bias for use in PICMG Hot Swap applications. Non-Hot Swap applications should pull this signal high. MARB_IN I MARB_OUT O8 0 ALE ADS BLAST READY WNR SDA SCL IOC[11:0] INT[3:0] O8 O8 O8 I O8 I/OD O2 I/O8 I/O8 Z Z Z RSTOUT O8 0 CH I 4 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC Table 3: Signal Descriptions (cont'd) MODE Input: selects mastership of V370PDC: MODE I 0 = Secondary master 1 = Primary master Power and Ground Signals Signal VCC GND NC Type R Description POWER leads for external connection to a 3.3V VCC board plane. GROUND leads for external connection to a GND board plane. No connect. a. R indicates state during reset. 2.1 Pinout Table 4 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 5 V370PDC Table 4: Pin Assignments PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal RSTIN PCLK GND Vcc NC CH AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 GND C_BE3 IDSEL AD23 AD22 Vcc AD21 AD20 AD19 AD18 AD17 AD16 GND C_BE2 FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR Vcc C_BE1 AD15 GND PIN # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal Vcc AD14 AD13 AD12 AD11 AD10 AD9 AD8 C_BE0 MODE GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vcc GND MAD0 DCS0 MAD1 DCS1 MAD2 DCS2 MAD3 DCS3 MAD4 GND MAD5 MWE MAD6 CAS MAD7 RAS MAD8 MA14 GND PIN # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal Vcc MAD9 MA13 MAD10 MA12 MAD11 MA11 MAD12 MA10 GND MAD13 IOC11 MAD14 IOC10 MAD15 IOC9 MAD16 IOC8 MAD17 Vcc GND MA9 MAD18 MA8 MAD19 MA7 MAD20 MA6 MAD21 GND MAD22 IOC7 MAD23 IOC6 MAD24 IOC5 MAD25 IOC4 MAD26 GND PIN # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal Vcc MA5 MAD27 MA4 MAD28 MA3 MAD29 MAD30 MAD31 GND MA2 MA1 MA0 IOC3 IOC2 READY MARB_OUT MARB_IN ADS Vcc GND CLKIN IOC1 IOC0 DQM3 DQM2 DQM1 DQM0 BLAST WNR GND CLKOUT RSTOUT ALE SDA SCL INT0 INT1 INT2 INT3 6 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC Figure 1: Pinout for 160-pin EIAJ PQFP (top view) Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 7 V370PDC Figure 2: 160-pin EIAJ PQFP mechanical details 8 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC 3.0 DC Specifications The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.2 Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification. Table 5: Absolute Maximum Ratings Symbol VCC VIN TSTG Parameter Supply voltage DC input voltage Storage temperature range Value -0.3 to +3.6 -0.3 to 6.0 -55 to +125 Units V V C Table 6: Guaranteed Operating Conditions Symbol VCC Jmax Parameter Supply voltage Maximum junction temperature Value 3.0 to 3.6 125 41 to 46 21 -40 to +85 Units V C C/w C/w C Theta Ja Thermal resistance (Package) Theta Jc Thermal resistance (Junction-Case) TA Ambient temperature range 3.1 PCI Bus DC Specifications Table 7: PCI Bus Signals DC Operating Specifications Symbol VIH VIL IIH IIL VOH VOL CIN CCLK Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Input pin capacitance PCLK pin capacitance Condition Min 0.5VCC -0.5 0.7VCC Max VCC + 0.5 0.3VCC Units V V A Notes 1 1 0 < VIN < VCC IOUT = -500A IOUT = 1500A 0.9VCC +10 A V 0.1VCC 10 5 12 V pF pF 2 3 Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 9 V370PDC Table 7: PCI Bus Signals DC Operating Specifications Symbol CIDSEL LPIN Parameter IDSEL pin capacitance Pin inductance Condition Min Max 8 20 Units pF nH Notes 4 Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 3.2 Local Bus DC Specifications Table 8: Local Bus Signals DC Operating Specifications (VCC = 3.3V+ 0.3V) Symbol VIH VIL IIH IIL VOH VOL IOZL IOZH ICC (max) ICC (typ) CIO Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Low level float input leakage High level float input leakage Maximum supply current Typical supply current Input and output capacitance VIN = VCC VIN=GND IOUT = -2, -8, -12mA IOUT = 2, 8, 12mA VOL = GND VOH = VCC PCLK=33MHz, CLKIN=66MHz, Vcc=3.6v, all buses operating -10 -10 -10 -10 2.4 0.4 10 10 70 40 10 Condition Min 2.0 0.8 10 10 Max Units V V A A V V A A mA mA pF 10 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC 3.3 AC Specifications The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification. 3.4 PCI Bus Timings Table 9: PCI Bus Signals AC Operating Specifications Symbol Parameter Switching Current high Condition 0V< VOUT 0.3VCC 0.3VCC Max Units mA mA Notes IOH(AC) (Test point) Switching Current low IOL(AC) (Test point) Low clamp current Unloaded output rise time Unloaded output fall time Equation C -32VCC 16VCC 26.7VCC 38VCC mA mA VOUT = 0.7VCC VCC > VOUT >0.6VCC 0.6VCC > VOUT >0.1VCC VOUT=0.18VCC -3V ICL mA tR 0.2VCC to 0.6VCC 1 4 V/ns tF 0.6V to 0.2V 1 4 V/ns Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 11 V370PDC 3.5 Local Bus Timings Table 10: Local Bus AC Test Conditions Symbol VCC VIN COUT Parameter Supply voltage 3.3 volt operation Input low and high voltages Capacitive load on output and I/O pins Limits 3.0 to 3.60 0.4 and 2.0 50 Units V V pF Table 11: Capacitive Derating for Output and I/O Pins Output Drive Limit 8mA 12mA Supply voltage 3.3 volt 3.3 volt Derating 0.019 ns/pF for loads > 50pF 0.017 ns/pF for loads > 50pF Figure 3: Clock and Synchronous Signals : 12 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. V370PDC Table 12: Local Bus Timing Parameters for Vcc =3.3 Volts +/- 5% 66MHz # 1 2 3 4 4a 5 6 7 8 9 10 11 Symbol TC TCH TCL TSU TSU TH TCOV TCZO TCOZ TALE TCLH TAH CLKIN period CLKIN high time CLKIN low time Synchronous input setup Asynchronous input setup (READY) Synchronous input hold CLKIN to output valid delay CLKIN to output driving delay CLKIN to high impedance delay ALE Pulse Width CLKIN rising to ALE rising CLKIN falling to ALE falling 1 Description Notes Min 15 5.5 5.5 3 7 1 3 3 4 TCH+0.5 2 2 11 11 12 TCH+1 10 10 Max Units ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Applies only to READY pin when i960_RDY bit in LB_BUS_CFG register is set to '1'. Table 13: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10% # 1 2 3 4 5 6 7 Symbol TC TSU TH TCOV TCZO TCOZ TRST PCLK period Synchronous input setup to PCLK Synchronous input hold from PCLK PCLK to output valid delay PCLK to output driving delay PCLK to high impedance delay Reset period when PRST used as input 2 1 Description Notes Min 30 7 0 3 4 5 16*TC 11 11 18 Max Units ns ns ns ns ns ns Copyright (c) 1999, V3 Semiconductor Corp. V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 13 V370PDC 3.6 Serial EEPROM Port TImings The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 4. Figure 4: Serial EEPROM Waveforms and Timings 512 PCI BUS CLOCKS STOP CONDITION START CONDITION SCL SDA 256 PCI BUS CLOCKS 256 PCI BUS CLOCKS 4.0 Revision History Table 14: Revision History Revision Number 0.8 Date Comments and Changes 01/99 First pre-silicon revision of preliminary data sheet. Update Figure 2: Mechanical Drawing; Update Table 8: Local Bus Signals DC Operating Specifications; Update Table 10: Local Bus AC Test Conditions; Update Table 12: Local Bus Signals AC Operating Specifications. Initial Release. Updated TBA parameters 0.9 03/99 1.0 1.1 03/99 06/00 USA: 2348G Walsh Avenue Santa Clara, CA 95051 Phone: (408)988-1050 Fax: (408)988-2601 Toll Free: (800)488-8410 (Canada and U.S. only) World Wide Web: http://www.vcubed.com 14 V370PDC_A0 Data Sheet Rev 1.01 DS-PD01-0101 Copyright (c) 1999, V3 Semiconductor Inc. |
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